Revision [6641]
This is an old revision of Abel made by ToBo on 2008-11-28 04:17:48.
Abel
abl2edif: version M1.5.25 -- Xilinx ABEL Software
Copyright (c) 1996 Xilinx Inc. All Right Reserved.
7-Segment-Anzeige
D:\fh\praktikum\digitaltechnik_4sem\v4\XILINX\ABL\ZU_V42
module Seg7dec title '7Segment' declarations A0 PIN; A1 PIN; A2 PIN; A3 PIN; SEG0 PIN istype 'reg'; SEG1 PIN istype 'reg'; SEG2 PIN istype 'reg'; SEG3 PIN istype 'reg'; SEG4 PIN istype 'reg'; SEG5 PIN istype 'reg'; SEG6 PIN istype 'reg'; equations SEG0 = (!A0# A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0#!A1#!A2# A3) & ( A0#!A1# A2#!A3) & (!A0#!A1#!A2#!A3); SEG1 = ( A0#!A1# A2# A3) & ( A0# A1#!A2#!A3) & ( A0#!A1#!A2#!A3) & (!A0#!A1#!A2#!A3); SEG2 = (!A0# A1# A2# A3) & (!A0#!A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0# A1#!A2# A3) & (!A0#!A1#!A2# A3) & (!A0# A1# A2#!A3); SEG3 = ( A0# A1# A2# A3) & (!A0# A1# A2# A3) & (!A0#!A1#!A2# A3) & ( A0# A1#!A2#!A3); SEG4 = (!A0# A1#!A2# A3) & ( A0#!A1#!A2# A3) & (!A0#!A1# A2#!A3) & ( A0# A1#!A2#!A3) & ( A0#!A1#!A2#!A3) & (!A0#!A1#!A2#!A3); SEG5 = (!A0# A1# A2# A3) & ( A0#!A1# A2# A3) & (!A0#!A1# A2# A3) & (!A0#!A1#!A2# A3) & (!A0# A1#!A2#!A3); SEG6 = (!A0# A1# A2# A3) & ( A0# A1#!A2# A3) & (!A0#!A1# A2#!A3) & (!A0# A1#!A2#!A3); end Seg7dec
Multiplexer
module V043 Title 'MUX' declarations A PIN; B PIN; C PIN; Y PIN istype 'reg'; Z PIN istype 'reg'; V PIN istype 'reg'; S PIN istype 'reg'; aIn = [A,B,C]; aOut = [Y,Z,V,S]; equations when (!A & !B & !C) then aOut=[0,0,0,0] else when (A & !B & !C) then aOut=[1,0,0,0] else when (A & B & !C) then aOut=[0,1,0,0] else when (A & B & C) then aOut=[0,0,1,0] else aOut=[0,0,0,1] test_vectors ([A,B,C] -> [Y,Z,V,S]) [0,0,0] -> [0,0,0,0]; [0,0,1] -> [0,0,0,1]; [0,1,0] -> [0,0,0,1]; [0,1,1] -> [0,0,0,1]; [1,0,0] -> [1,0,0,0]; [1,0,1] -> [0,0,0,1]; [1,1,0] -> [0,1,0,0]; [1,1,1] -> [0,0,1,0]; end V043
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